1. Field of the Invention
This invention relates to a dry etching method employed for the preparation of a semiconductor device. More particularly, it relates to a method for planarizing minute irregularities or steps produced on the surface of a silicon based or silicon oxide based material.
2. Description of Related Art
In keeping up with the recent tendency towards high integration and high performance of semiconductor devices, such as VLSIs or ULSIs, more and more strict technical demands have been raised on various preparation processes. Above all, in the field of dry etching, various effects which have not been produced under the former design rule have come to the surface, whilst minute surface irregularities or steps, which have been neglected as being not worthy of note, have been found to affect the process. For example, new problems have been raised in connection with unusual contours produced at the bottom of contact holes or trenches, deteriorations in the surface morphology of layers of a variety of materials or planarities of interlayer insulating films in multi-level interconnections. These will be discussed in sequence.
The first problem of unusual contours in contact holes or at the trench bottom has been presented as a counter-effect of the measures taken for preventing microloading effects. The microloading effects means a phenomenon in which, when there exist plural apertures of different diameters on a substrate, the etching rate is diminished significantly in smaller apertures. The conventional practice for reducing the phenomenon is to lower the gas pressure during etching. In this manner, the mean free path of the ions is extended to increase the energy of incident energy as well as the vertically incident component to lower the aperture diameter dependency of the etching rate.
However, with the etching under reduced gas pressure, an unusual cross-sectional shape known as trenching tends to be produced. This trenching is a phenomenon in which an incision known as a sub-trench is apt to be produced at a corner of the trench which is formed by etching the single crystal silicon substrate by means of an etching mask formed of a sllicon oxide layer. Although the mechanism of trenching is not known precisely, it is possibly ascribable to the presence of ions which are incident from an oblique direction due to scattering at an edge of a mask which has become receded under ion sputtering, to a deposition of etching by-products to an increased thickness at the middle of the trench bottom, and to an increased etching rate in the vicinity of the sidewall on which the amount of the deposit is small due to the increased vertically incident component thereon under a low gas pressure. If the processes of element isolation or formation of capacitor elements are to be initiated at this stage, various inconveniences would be produced, such as lattice defects within the single crystal silicon substrates during the annealing process.
Similar trenching may be produced when forming contact holes by etching a silicon oxide interlayer insulating film with a single crystal substrate as an underlying layer. If overetching should be performed in this state, the contour of the sub-trench produced at the contact hole would be reflected in the underlying single crystal silicon substrate, so that lattice defects or the like again tend to be produced.
The present Assignee has hitherto proposed techniques for trimming the trenching.
As to silicon trench etching, there is disclosed in JP Patent KOKAI Publication No. 63/491 (1988) a technique of etching a silicon substrate, using a chlorine-based gas, such as Cl.sub.2, to a depth slightly less than a desired depth, and etching to the desired depth using a gas which is the above mentioned chlorine-based gas with an addition of a deposition gas, such as CH.sub.2 F.sub.2. According to this technique, the bottom surface of the trench may be planarized because etching proceed competitively whilst the sub-trench is protected by a carbonaceous polymer.
On the other hand, as to etching of a contact hole, there has recently been proposed a technique of etching a silicon oxide interlayer insulating film, using a gas composed essentially of a compound enabling a ion mode etching, such as C.sub.3 F.sub.8 , to a point slightly before the underlying layer is exposed, allowing the carbonaceous polymer to be deposited in the sub-trench using a deposition gas such as CH.sub.2 F.sub.2, and then etching the carbonaceous polymer and the remaining portion of the silicon oxide interlayer insulating film using CHF.sub.3. Alternatively, deposition of the carbonaceous polymer and the etching of the silicon oxide interlayer insulating film may be caused to proceed competitively, even if CHF.sub.3 is used alone from the outset, subject to certain minor changes of the operating conditions.
The second problem is deterioration of the surface morphology of the layers of various materials, and is presented when forming, for example, a layer of refractory metal silicide by high temperature CVD. The layer of the refractory metal silicide has been used extensively in recent years as a gate electrode material in the form of a stacked layer with a doped polysilicon layer. Typical of the refractory metal silicide layer is a tungsten silicide (WSi.sub.x) layer making use of tungsten as refractory metal.
The method for forming the WSi.sub.x layer may be roughly classified into a low temperature CVD method and a high temperature CVD method. The low temperature CVD method is a technique of allowing WSi.sub.x to be deposited by a mixed gas of SiH.sub.4 and WF.sub.6 for example while maintaining the wafer temperature of approximately 360.degree. C. The high temperature CVD method is a technique of allowing WSi.sub.x to be deposited by a mixed gas of SiH.sub.2 Cl.sub.2 and WF.sub.6 for example while maintaining the wafer temperature of approximately 600.degree. C. As compared to the low temperature CVD method, the high temperature CVD method has such advantages that the produced WSi.sub.x layer is low in the fluorine content and exhibits strong adhesion properties with respect to the underlying doped polysilicon layer and superior step coverage as well as lesser temperature dependency of the internal stress.
However, the WSi.sub.x layer produced by the high temperature CVD method suffers from rather severe surface irregularities, as will be discussed subsequently. Since WSi.sub.x is naturally deposited during the high temperature CVD process on an alignment mark used for photomask position matching, it becomes difficult to detect the reflected light. Besides, the photoresist layer exhibits nonuniform thickness on such a WSi.sub.x layer, so that accuracy in photolithgraphy may be lowered. If the WSi.sub.x layer is etched with the severe surface irregularities remaining intact, the subsequent operating steps may be affected due to, for example, transfer of the surface irregularities onto the surface of the underlying layer.
Deterioration in the surface morphology presents problems not only in the WSi.sub.x layer produced by the above mentioned CVD method, but also in trench sidewalls used for forming capacitative elements or in polysilicon layers used for forming gate electrodes of PMOS transistors functioning as load resistor elements for SRAMs. In these cases, if the surface irregularities are left unattended, the oxide film formed thereon tends to be non-uniform and to lower the voltage resistance. Planarization is a desideratum in a large number of material layers in the preparation of semiconductor devices, and several techniques to meet the demands have been proposed.
For example, in Extended Abstracts of the 35th Sprlng Meeting (1988) of the Japan Society of Applied Physics and Related Societies, page 498, lecture number 28p-G-2, a report has been made of a technique of etching a previously trenched silicon substrate in a downflow type chemical dry etching device, using a mixed gas of CF.sub.4 and O.sub.2, for rounding trench corners and smoothing sidewall roughnesses for improving the voltage resistance of the oxide film.
Also, in Extended Abstracts of the 35th Spring Meeting (1989) of the Japan Society of Applied Physics and Related Societies, page 572, lecture number 1p-L-8, a report has been made of a technique of smoothing a polysilicon layer by a similar gas system. In this case, the voltage resistance of the oxide film produced by surface oxidation of polysilicon is improved significantly.
In these techniques, O.sub.2 is used in excess relative to CF.sub.4 for yielding a silicon oxyfluoride Si.sub.x F.sub.y O.sub.z and the silicon substrate or the polysilicon layer is smoothed by competitive processes of Si.sub.x F.sub.y O.sub.z deposition and etching reactions. It is premeditated that such smoothing is realized by a mechanism in which the vapor pressure of Si.sub.x F.sub.y O.sub.x ls low on a surface of negative curvature such as trench corners or surface recesses to suppress etching to favor deposition while the vapor pressure of Si.sub.x F.sub.y O.sub.z is high on a surface of positive curvature such as surface projections to favor etching rather than deposition.
The third problem is insufficient planarity of the interlayer insulating film. In keeping up with the accelerated progress in recent years to higher integration and higher density of semiconductor devices, an increasing area tends to be taken up by interconnections on a device chip so that multi-level interconnections are becoming indispensable for preventing a chip area from being increased. Hence, planarization of the interlayer insulating film has become more crucial for maintaining processing accuracy and step coverage of the interconnection layer in the course of the subsequent processing steps.
The commonplace practice in planarizing the interlayer insulating film has been to form a planar layer of a resist material on the surface of the interlayer insulating film and to etch back the layer of the resist material and the interlayer insulating film at an equal etchrate.
In an Extract of VLSI Multilevel Interconnection Conference (1989) pages 89 to 98, there is disclosed a method of planarizing the substrate by a B.sub.2 O.sub.3 planarizing film followed by etchback at an equal etchrate. The planarizing film may be produced in an extremely planar state by introducing trimethyl borate B(OCH.sub.3).sub.3, a liquid substance at ambient temperature, into a plasma CVD device, along with O.sub.2, to then al low B.sub.2 O.sub.3 to flow and be precipitated on the wafer surface with the wafer temperature of 390.degree. to 480.degree. C.
There is also proposed a technique of coating the interlayer insulating film with a low molecular weight styrene-chloromethylstyrene polymer solution to planarize the substrate surface to effect etchback at an equal etching rate after the drying and cross-linking steps.
Although demands have been raised for planarization and smoothing for the preparation of semiconductor devices, the conventional techniques leave much to be desired.
In the technique of allowing the carbonaceous polymer to be deposited for trimming the trench, the polymer is deposited on any components present in an etching chamber at the same time that it is deposited on a substrate, so that the risk of pollution by particles is increased. Above all, when processing a number of wafers one by one, higher levels of pollution by particles are encountered with the progress of the processing operations.
The technique of allowing Si.sub.x F.sub.y O.sub.z to be deposited for improving the surface morphology is similarly not exempt from the problem of pollution by particles.
With the technique of planarizing the interlayer insulating film by B.sub.2 O.sub.3, meticulous attention needs to be exercised in controlling the atmosphere within the etching device to complicate the operation because of the high hygroscopicity of B.sub.2 O.sub.3 and the high softening point thereof which is as high as about 460.degree. C. If the metal interconnection is of aluminum, the interconnection may be deteriorated. If a styrene-chlorostyrene polymer is used, pollution tends to be produced during drying and crosslinking, while the throughput may also be lowered.